The waveform for the simulation results is below.
#Pre timer eon timer code#
The simulation test bench code for this project is available on github. Wire scalerNext Īssign scalerNext = (rScaler = 2 ** ps - 1) ? 0 : (rCounter = 0) ? 0 : rScaler + 1 Īssign counterNext = (rCounter = 0) ? d_in : (scalerNext = 0) ? rCounter - 1 : rCounter Output tick // tick event raised when timer reaches zero configurable timer module with pre-scaler And finally, if neither of those cases are true, then scalerNext is given the current value of rCounter. Otherwise, counterNext is given the value rCounter – 1 if scalerNext is 0, which happens when the pre-scaler reaches its limit. This code says that the value of counterNext is d_in if rCounter has reached 0. On line 46 you can see that the logic for computing counterNext has also become a little more complicated. If neither of those two conditionals are true, then I set the value of scalerNext to rScaler + 1. Otherwise the value of scalerNext is 0 if rCounter has reached 0. For a pre-scaler an input of 4 the limit is 15 (2 ** 4 – 1). The code says that the value of scalerNext is 0 if rScaler has reached its limit of 2 ** ps – 1. This code looks tricky because it is a conditional within a conditional. Starting on line 43 you can see how I calculate the value of scalerNext. The most interesting part of the pre-scaler is the combinational logic which drives both the pre-scaler counter and the timer itself.
#Pre timer eon timer update#
To the always block starting on line 30 I add logic to zero the scaler register on rst, and to update the scaler on each clock tick only if en is true. Note that in this code I’ve renamed rNext to counterNext for clarity These show up on lines 21 and 27 respectively. I’ll call these signals reg rScaler and wire scalerNext. I will add this in the form of a register and some interconnect signals to drive that logic. Since the pre-scaler is effectively a counter the divides the clock input we must add some additional state to drive the counter logic. The next change is the addition of the pre-scaler input port ps at line 12. This parameter represents how many bits of pre-scaler input the timer accepts. The first change is the addition of a new configuration parameter I call SCALER_BITS which defaults to 2. If you want to peek ahead the complete code is shown below. In order to add a pre-scaler we need to make a few changes to the Timer code. reset timer when it reaches zero, otherwiseĪssign rNext = (rCounter = 0) ? d_in : rCounter - 1 Īssign tick = (rCounter = 0) ? 1'b1 : 1'b0 only update counter when it is enabled update or reset the timer on the clock tick holds the next value of internal counter Output tick // tick event raised when counter reaches zero For reference, below is the complete Verilog code for the countdown timer. This requires fewer FPGA resources.īefore we dive into the changes required to add the pre-scaler let’s review the code from last time. So an input of 0 results in a clock divisor of 1 (2 ** 0), while an input of 4 results in a clock divisor of 16 (2 ** 4). The pre-scaler input value represents the power of 2 exponent of the divisor for the timer clock. And that cost scales linearly with the number of bits used by the timer. logic cells, input and output ports) than an 8-bit timer. While we can configure a 16-bit timer to count longer intervals, such a design costs more in terms of FPGA resources (ie. And so you might reasonably suggest that we simply create a timer using more bits, say 16-bits or 24, or more. With an 8-bit countdown timer we can only time 5 microsecond intervals.Īh, but you may rightly recall from last time that the bit-count of the timer we created is configurable. Therefore, an 8-bit countdown timer counts down from 255 to 0 in a little more than 5.1 microseconds (20ns/clock cycle * 256). And as a result, a clock cycle lasts only 20ns.
Remember that the Artix-7 FPGA on the Basys 3 runs at 100Mhz. What exactly is a pre-scaler? You can think of the pre-scaler as an integer value that scales (or divides) the timer clock signal down to a lower frequency. Now I will add a pre-scaler to the Timer. Previously I designed a simple configurable countdown Timer with asynchronous reset, enable and limit.
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